SystemVerilog .* Notation

A customer asked me what would happen if a variable didn't exist when using the SystemVerilog .* port notation. Actually, I knew the answer to this, but forgot I did, so did a little EDA Playground test to see:

module DUT (input i, output o);
  assign i = 0;
endmodule

module T;
  DUT dut (.*); 
endmodule

https://www.edaplayground.com/x/43KN

This is an error, because all variables required by the .* notation must exist. It also does strict type checking, so this will not compile, either:

module T;
  logic i; 
  int o;
  DUT dut (.*);
endmodule

because int is the wrong width.

A customer asked me about this. I didn't know the answer, so I wrote a few lines of code on EDA Playground. EDA Playground is great for that, because it's always on. You don't have to queue for licences, wait for EDA tools to start, create new files, fire up editors...

Comments

Post a Comment

Popular posts from this blog

Bit Width Casting in SystemVerilog

Image
I must have taught SystemVerilog more than 20 times. My customers this week are privileged: they are the first to be taught after I have thought of a use for SystemVerilog bit width casting : in Verilog (and hence SystemVerilog), the simulator (and hence the synthesiser) must decide how many bits to use when calculating an arithmetic expression. This     logic [7:0] A, B, F;     F = (A * B) >> 8; is an example of a so-called context sensitive expression . With a context sensitive expression, the simulator looks at the widths of the operands (to the right of the assignment operator) and the result (to its left) and finds the widest. It then uses this as the number of bits to use in the calculation. So, in the example above, the simulator will look at the widths of A , B and F , discover that they are all 8, and so will do 8-bit arithmetic. (So, it is highly likely that the result of (A * B) will be truncated, because the result of the multiplication will be truncated to
Read more

How to convert a std_logic_vector to a hex string?

I was asked how to easily convert a std_logic_vector to a hex string . This is easy: there's a procedure in the ieee.std_logic_textio package caled hwrite which does most of the hard work for us. The ieee.std_logic_textio package is an add on to the std.textio package, which enables std_logic and associated types to be written to files (you need both packages to do this). Both packages first write to a variable of type line , which is declared in the textio package. The line type is an access type , which points to a string ; this is a line of code from the textio package: type line is access string;         So, let's write a function to convert a std_logic_vector to a string . Our input is a std_logic_vector and our return value is a string : function to_hstring (SLV : std_logic_vector) return string is Notice that both the function input and the return type are unconstrained - they are arrays with no bounds. This is legal for function inputs and return type
Read more

Can you add/remove more than 1 item from a queue?

Can you add more than one item to a SystemVerilog queue using the concatenation operator? Yes, you can. Here's some code: module M;     initial begin     // Here's a queue, initialised with 3 members. (And a maximum     // index of 8 - more on that story later).     int i, numbers[$:8] = {1,2,3};         // Let's add a member to the front and another to the back     // using concatenation.       numbers = {numbers, 4};      $display("numbers= %p", numbers);     numbers = {0, numbers};      $display("numbers= %p", numbers);         // I told you you couldn't do this. I don't know where I got     // that idea from. (I do remember trying and it not working).     // Anyway, it works.       numbers = {numbers, 5, 6};   $display("numbers= %p", numbers);     numbers = {-2, -1, numbers}; $display("numbers= %p", numbers);         // We know we can do this.     numbers = numbers[1:$];      $display("numbers= %p", number
Read more