EDA Playground

Can you add more than one item to a SystemVerilog queue using the concatenation operator? Yes, you can. Here's some code: module M;     initial begin     // Here's a queue, initialised with 3 members. (And a maximum     // index of 8 - more on that story later).     int i, numbers[$:8] = {1,2,3};         // Let's add a member to the front and another to the back     // using concatenation.       numbers = {numbers, 4};      $display("numbers= %p", numbers);     numbers = {0, numbers};      $display("numbers= %p", numbers);         // I told you you couldn't do this. I don't know where I got     // that idea from. (I do remember trying and it not working).     // Anyway, it works.       numbers = {numbers, 5, 6};   $display("numbers= %p", numbers);     numbers = {-2, -1, numbers}; $display("numbers= %p", numbers);         // We know we can do this.     numbers = numbers[1:$];      $display("numbers= %p", number

A customer asked me whether a class's randomize method could be overridden. I said I didn't know - I will find out. As is often the case, to find out I wrote a few lines of code on EDA Playground. EDA Playground is great for that, because it's always on. You don't have to queue for licences, wait for EDA tools to start, create new files, fire up editors... So, I wrote this: module override_randomize;     class C;     rand int i;   endclass     class E extends C;     rand int another_i;     function bit randomize;       return super.randomize;     endfunction     function new;       super.new;     endfunction   endclass         initial begin     C c = new;     E e = new;     void'(c.randomize); $display(c.i);     void'(e.randomize); $display(e.another_i);   end   endmodule https://www.edaplayground.com/x/2G8z and found out that the randomize method can't be overridden: ERROR VCP2949 "The randomize() is a predefined method in class and cannot be

A student asked me whether it was possible to have a recursive function in Verilog. This set me wondering whether it was possible to do recursive instantiation in Verilog. Recursive instantiation is where a module instantiates itself. Why would you want to do that? Well, some problems lead themselves to a recursive solution. Finding the minimum of a set of numbers is just such a job: basically, the minimum of a set of numbers is the minimum of the minimum of the first half and the minimum of the second half. Run that by me again... Take a set of numbers. Divide that set in half. Find the minimum of each half. The minimum of the whole set is the lesser of the minimums of each half. How do you find the minimum of each half? Well, each half is a set of numbers, so for each half, go back to the beginning of this paragraph... See: it's recursive. Eventually, you get a set of one number. The minimum of that set is obviously that number, so the problem becomes trivial, which is the