How to convert a std_logic_vector to a hex string?
I was asked how to easily convert a std_logic_vector
to a hex string. This is easy:
there's a procedure in the ieee.std_logic_textio
package caled hwrite which does
most of the hard work for us. The ieee.std_logic_textio
package is an add on to the std.textio
package, which enables std_logic
and associated types to be written to files (you need both packages to do
this). Both packages first write to a variable of type line, which is declared in the textio package. The line
type is an access type, which points to a string;
this is a line of code from the textio
package:
type line is access string;
So, let's write a function to convert a std_logic_vector to a string. Our input is a std_logic_vector and our return value is a string:
function to_hstring (SLV : std_logic_vector) return string is
Notice that both the function input and the return type are unconstrained - they are arrays with no bounds. This is legal for function inputs and return types in VHDL and is clearly useful here: it would be impractical to have to write separate functions for each different length of input std_logic_vector.
Next we're going to need a (local) variable of type line to store the output from the hwrite procedure:
variable L : LINE;
Now we call the hwrite procedure, which writes the std_logic_vector to the line variable:
hwrite(L,SLV);
So, the hard work has been done. We have converted our std_logic_vector to a hex string. We just need to get at it. Our line variable (L) is an access type - a pointer to a string. We need to get at the memory where it is pointing. We do this by dereferencing the pointer. This is done in VHDL by adding .all to our line variable L. And, finally, we just need to return this from our function. We don't need to worry about the string length, because our return value is unconstrained:
return L.all;
And that's it. A simple function to convert a std_logic_vector to a hex string:
function to_hstring (SLV : std_logic_vector) return string is
variable L : LINE;
begin
hwrite(L,SLV);
return L.all;
end function to_hstring;
There is also a plain write procedure in the std_logic_textio package, which writes the std_logic_vector is binary and, should you ever need it, an owrite procedure for octal.
One last thing. Notice we're calling a procedure (hwrite) from a function. That is legal in VHDL as long as the procedure has no wait statements in it. (A VHDL function cannot include a wait statement.)
You can see this code on EDA Playground at https://www.edaplayground.com/x/6_VZ .
type line is access string;
So, let's write a function to convert a std_logic_vector to a string. Our input is a std_logic_vector and our return value is a string:
function to_hstring (SLV : std_logic_vector) return string is
Notice that both the function input and the return type are unconstrained - they are arrays with no bounds. This is legal for function inputs and return types in VHDL and is clearly useful here: it would be impractical to have to write separate functions for each different length of input std_logic_vector.
Next we're going to need a (local) variable of type line to store the output from the hwrite procedure:
variable L : LINE;
Now we call the hwrite procedure, which writes the std_logic_vector to the line variable:
hwrite(L,SLV);
So, the hard work has been done. We have converted our std_logic_vector to a hex string. We just need to get at it. Our line variable (L) is an access type - a pointer to a string. We need to get at the memory where it is pointing. We do this by dereferencing the pointer. This is done in VHDL by adding .all to our line variable L. And, finally, we just need to return this from our function. We don't need to worry about the string length, because our return value is unconstrained:
return L.all;
And that's it. A simple function to convert a std_logic_vector to a hex string:
function to_hstring (SLV : std_logic_vector) return string is
variable L : LINE;
begin
hwrite(L,SLV);
return L.all;
end function to_hstring;
There is also a plain write procedure in the std_logic_textio package, which writes the std_logic_vector is binary and, should you ever need it, an owrite procedure for octal.
One last thing. Notice we're calling a procedure (hwrite) from a function. That is legal in VHDL as long as the procedure has no wait statements in it. (A VHDL function cannot include a wait statement.)
You can see this code on EDA Playground at https://www.edaplayground.com/x/6_VZ .
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