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Q : If you write     F <= A and B or C and D; in VHDL. What do you get? A : An error message. eg In Riviera Pro*: COMP96 ERROR COMP96_0661: "Expression with a sequence of different logical operators is not allowed. Parenthesize subexpressions containing and, or, xor, and xnor operators." "testbench.vhd" 15 16 This might explain why I had no clue about logical operator precedence in VHDL. -- *other simulators are available A customer asked me about this. I didn't know the answer, so I wrote a few lines of code on EDA Playground. EDA Playground is great for that, because it's always on. You don't have to queue for licences, wait for EDA tools to start, create new files, fire up editors...

I haven't been teaching much VHDL recently. This isn't some valuable marketing insight - Doulos still sell a lot of VHDL courses - it's just I haven't been teaching it much. So, most of the stuff so far is SystemVerilog related. I'm sure they'll be more VHDL coming up...

A customer asked me what would happen if a variable didn't exist when using the SystemVerilog .* port notation. Actually, I knew the answer to this, but forgot I did, so did a little EDA Playground test to see: module DUT (input i, output o);   assign i = 0; endmodule module T;   DUT dut (.*);  endmodule https://www.edaplayground.com/x/43KN This is an error, because all variables required by the .* notation must exist. It also does strict type checking, so this will not compile, either: module T;   logic i;    int o;   DUT dut (.*); endmodule because int is the wrong width. A customer asked me about this. I didn't know the answer, so I wrote a few lines of code on EDA Playground. EDA Playground is great for that, because it's always on. You don't have to queue for licences, wait for EDA tools to start, create new files, fire up editors...

I was asked what would have if, in a class derived from a UVM uvm_sequence_item class, one overrode the do_copy method and also specified a copy method using the field macros . I said I think I knew, because I knew exactly what would happen if the case of the compare method and that I expected the same behaviour with the copy method. However, it pays to confirm this by having a play on EDA Playground . So, what would happen with the compare method? Well, (i) both methods would be called and (ii) the field macro method would be called first and (iii) the result from each would be ANDed together. So, what would happen with the copy method? I wrote some code to find out. Here is a class derived from a uvm_sequence_item class, with overridden do_compare and do_copy methods and field macros that also specified both. It turns out that, just like with compare , (i) both methods would be called and (ii) the field macro method would be called first. https://www.edaplayground....

A customer asked me a couple of questions about how SystemVerilog enum base type values are assigned: Here is a line from the Doulos Comprehensive SystemVerilog course: enum { aa, bb, cc, dd = 7, ee, ff, gg = 6, hh = 5 } variable; The base type of this enum is int (by default). The values assigned to the values are these aa  0  default for base type (int) bb  1  next value cc  2  next value dd  7  explicitly set ee  8  next value ff  9  next value gg  6  explicitly set hh  5  explicitly set So, if we said enum { aa, bb, cc, dd = 7, ee, ff, gg = 6, hh = 5, ii } variable; What would be the value of ii ? The answer is that it wouldn't compile, because a value of 6 would be assigned to ii (because that's the next value after 6) and that is no good because it's already taken (by hh ). So, how about this case? typedef enum logic {zero, one, ex, zed} logic_enum; This won't compil...

A customer asked me whether it was possible to have a pointer to a pointer in VHDL. In other words, is it possible to have an access type that points to another access type ? I did a little experiment on EDA Playground and it turns out that it is. Here's an access type to an integer:     type ai is access integer; and here's an access type to that access type:     type aai is access ai; and here are variables to both:     variable aiv : ai;     variable aaiv : aai; So, let's allocate memory for both:     aiv := new integer'(6);     aaiv:= new ai'(aiv); and then dereference each:     report "aiv.all= " & integer'image(aiv.all);     report "aaiv.all.all= " & integer'image(aaiv.all.all); Yes, aaiv.all.all ! Here's all the code and the EDA Playground link: https://www.edaplayground.com/x/4USx entity E is end entity ; archite...

We were discussing the difference between static and automatic variables in a SystemVerilog class. Whether a variable is static and automatic is called its lifetime . IEEE 1800-2012 gives the syntax for a variable declaration: data_declaration10 ::= [ const ] [ var ] [ lifetime ] data_type_or_implicit list_of_variable_decl_assignments ; | type_declaration A static variable exists for the whole simulation; an automatic variable exists only for the lifetime of the task, function or block - they are created when the task, function or block is entered and destroyed when it is left.  This has consequences: An automatic variable is initialized every time the task, function or block containing it is entered. When you think about it, how could it be any other way? The variable didn't exist until the task, function or block was entered. A static variable already exists before the task, function or block is entered and so is not initialized when that task, function or block is enter...