VHDL Logical Operator Precedence


Q: If you write

    F <= A and B or C and D;

in VHDL. What do you get?

A: An error message. eg In Riviera Pro*:

COMP96 ERROR COMP96_0661: "Expression with a sequence of different logical operators is not allowed. Parenthesize subexpressions containing and, or, xor, and xnor operators." "testbench.vhd" 15 16

This might explain why I had no clue about logical operator precedence in VHDL.

--

*other simulators are available

A customer asked me about this. I didn't know the answer, so I wrote a few lines of code on EDA Playground. EDA Playground is great for that, because it's always on. You don't have to queue for licences, wait for EDA tools to start, create new files, fire up editors...

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