Bit Width Casting in SystemVerilog
I must have taught SystemVerilog more than 20 times. My customers this week are privileged: they are the first to be taught after I have thought of a use for SystemVerilog bit width casting : in Verilog (and hence SystemVerilog), the simulator (and hence the synthesiser) must decide how many bits to use when calculating an arithmetic expression. This logic [7:0] A, B, F; F = (A * B) >> 8; is an example of a so-called context sensitive expression . With a context sensitive expression, the simulator looks at the widths of the operands (to the right of the assignment operator) and the result (to its left) and finds the widest. It then uses this as the number of bits to use in the calculation. So, in the example above, the simulator will look at the widths of A , B and F , discover that they are all 8, and so will do 8-bit arithmetic. (So, it is highly likely that the result of (A * B) will be truncated, because the result of the multiplication will be truncated to