Why bother with packages in SystemVerilog?


In SystemVerilog you are not allowed to use the same value for two different enums in the same scope. For example, this is not allowed:
  
typedef enum logic[1:0] {BRONZE, SILVER, GOLD} medal;
typedef enum logic[1:0] {BRONZE, SILVER, GOLD} metal;

So, what to do?

A SystemVerilog package is a scope. It has a name. That's the whole point of it. We can declare
 our two enums in different packages:

package P1;
  typedef enum logic[1:0] {BRONZE, SILVER, GOLD} medal;
endpackage

package P2;
  typedef enum logic[1:0] {BRONZE, SILVER, GOLD} metal;
endpackage

so now, they are in different scopes. As long as we don't try to import everything in each package into the same scope, in other words, as long as we don't do this:

import P1::*;
import P2::*; 

but instead refer to each enum type and value using the scope resolution operator - :: - then we're OK:

module M;
  initial begin
    static P1::medal m1;
    static P2::metal m2;
    $display("m1= %b", m1);
    m1 = P1::BRONZE;
    m2 = P2::BRONZE;
    $display("m1= %b", m1);
  end
endmodule

https://www.edaplayground.com/x/5HHG

This is a good illustration of the whole point of having packages in SystemVerilog.

A customer asked me about this. I didn't know the answer, so I wrote a few lines of code on EDA Playground. EDA Playground is great for that, because it's always on. You don't have to queue for licences, wait for EDA tools to start, create new files, fire up editors... 

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