The difference between logic and var and reg

A customer asked me about the difference between logic and var and reg. I put together some examples on EDA Playground.

https://www.edaplayground.com/x/4VFy


You can do all these:

  logic only_logic;     obviously a logic, but is also a variable because everything
                        in SV is a variable if you don't declare it as a net
 
  reg only_reg;         obviously this is allowed - it's just good old-fashioned                         Verilog
 
  var logic var_logic;  obviously a variable and obviously a logic
                        Verilog

   var reg var_reg;      bizarrely this is allowed, too (it's like reg is a type)
 
but not this:

  reg logic reg_logic;   if reg is like a type, then this is like
                         logic logic - clearly nonsense

You can do all these:

  wire logic wire_logic;  obviously a wire (not a variable) of type logic

  wire only_wire;         and this is also obviously a wire (and is type 
                          logic by default)

but not this:

  wire reg reg_wire;      surely no surprise there
 
A customer asked me about this. I didn't know the answer, so I wrote a few lines of code on EDA Playground. EDA Playground is great for that, because it's always on. You don't have to queue for licences, wait for EDA tools to start, create new files, fire up editors...

Comments

  1. OutputLogic16 February 2019 at 04:58

    Just wanted to add one more thing: the difference between "logic" and "wire".
    "wire a=b" is equivalent to "wire a; assign a=b".
    But "logic a=b" does not have the same behavior. It does initialization, but not continuous assignment.
    According to the SystemVerilog spec: "unlike nets, a variable cannot have an implicit continuous assignment as part of its declaration".

    ReplyDelete

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