EDA Playground

A customer asked me "can I have a coverpoint for a transaction?" What? Well, we might use a class to represent a transaction. So, can we have a coverpoint for that? Let's see. Suppose we have a class , eg   class C;     bit b1, b2;   endclass   Can we do:   covergroup CG;     coverpoint c;   endgroup    The answer is no. But we are allowed to do this:   covergroup CG;     coverpoint c.b1;     coverpoint c.b2;   endgroup Here's what the Stack Overflow folks call an MCVE : module M;     class C;     bit b1, b2;   endclass     C c = new;     covergroup CG;   //coverpoint c;      // THIS WON'T COMPILE     coverpoint c.b1;     coverpoint c.b2;   endgroup     CG cg = new;   endmodule https://www.edaplayground.com/x/ZV_ A customer asked me about this. I didn't know the answer, so I wrote a few lines of code on EDA Playground. EDA Playground is great for that, because it's always on. You don't have to queue for licences, wait for EDA tools to

I was asked; "Is a class virtual because it is marked as such or because it contains at least one pure virtual method?" Hmmm... Good question. Let's find out. This code compiles fine: module M;     class base_class;     virtual function void foo; endfunction   endclass         base_class p = new;       endmodule https://www.edaplayground.com/x/32HJ because the class base_class is not virtual. However, this does not: module M;     virtual class virtual_base_class;     virtual function void foo; endfunction   endclass         virtual_base_class p = new;       endmodule https://www.edaplayground.com/x/3RSk because the class is marked as virtual, even though it contains no pure virtual functions . This will not compile, either, because the class is not marked as virtual, but does contain a pure virtual function: module M;     class virtual_base_class;     pure virtual function void foo;   endclass             endmodule      https://www.edaplayground.com/x/

Last week I was asked a couple of questions about called base class constructors, to which I didn't know the answers. So, I did some digging. Firstly, Can you call super.new when there is no explicit constructor in the base class? To which the answer is: yes. I can't think why you'd want to, though. module M;     class C;     bit b;   endclass     class P extends C;     bit b;     function new;       super.new;     endfunction   endclass     C c = new;   endmodule https://www.edaplayground.com/x/3BB9 Can you call super.super.new? To which the answer is: no. Section 8.15 of IEEE 1800-2107 says "There is no way to reach higher (for example, super.super.count is not allowed)." module M;     class C;     bit b;   endclass     class P extends C;     bit b;   endclass;     class GP extends P;     bit b;     function new;       super.super.new;    // this line is illegal       super.new;     endfunction   endclass;     initial begin     GP gp;     g

A customer asked me whether you have a generic virtual interface, which could point at any kind of interface? eg    virtual interface vif; instead of    virtual APB_if vif; I would be nice perhaps. And you'd think it might be possible, because generic interface ports are possible. (See IEEE 1800-2017, section 25.3.3). However, this is one of those questions that I realise I know the answer to as soon as I try to start answering it.    virtual APB_if vif; is actually short for    virtual interface APB_if vif; (ie the " interface " is optional). So, because of that,    virtual interface vif; is clearly nonsense. IEEE 1800-2017, section 25.9 shows the syntax of a virtual interface:     virtual [ interface ] interface_identifier [ parameter_value_assignment ] [ . modport_identifier ]     interface I;       bit b;     endinterface     module M;         I i ();         // This line is NG:       //virtual interface vif1 = i;        

A customer asked me whether you could extend a concrete class into an abstract class, by adding a pure virtual function. It turns out you can. IEEE 1800-2012 section 8.21 confirms this: Any class may be extended into an abstract class, and may provide additional or overridden pure virtual methods. module M;     virtual class pure_virtual_base_class;     pure virtual function void foo;   endclass     class concrete_class extends pure_virtual_base_class;     virtual function void foo; endfunction   endclass     virtual class another_pure_virtual_base_class extends concrete_class;     pure virtual function void foofoo;   endclass      endmodule    https://www.edaplayground.com/x/2FpZ A customer asked me about this. I didn't know the answer, so I wrote a few lines of code on EDA Playground. EDA Playground is great for that, because it's always on. You don't have to queue for licences, wait for EDA tools to start, create new files, fire up editors...

I must have taught SystemVerilog more than 20 times. My customers this week are privileged: they are the first to be taught after I have thought of a use for SystemVerilog bit width casting : in Verilog (and hence SystemVerilog), the simulator (and hence the synthesiser) must decide how many bits to use when calculating an arithmetic expression. This     logic [7:0] A, B, F;     F = (A * B) >> 8; is an example of a so-called context sensitive expression . With a context sensitive expression, the simulator looks at the widths of the operands (to the right of the assignment operator) and the result (to its left) and finds the widest. It then uses this as the number of bits to use in the calculation. So, in the example above, the simulator will look at the widths of A , B and F , discover that they are all 8, and so will do 8-bit arithmetic. (So, it is highly likely that the result of (A * B) will be truncated, because the result of the multiplication will be truncated to